1. Field of the Invention
Example embodiments relate to a method of forming a contact structure, and more particularly, to a method of forming a contact structure having an improved alignment margin.
A claim of priority is made to Korean Patent Application No. 2008-66858, filed Jul. 10, 2008, the contents of which are incorporated herein by reference.
2. Description of the Related Art
As semiconductor devices have become highly integrated, areas of unit cells have been greatly reduced, and also operational voltages have been lowered. Accordingly, design rules may be decreased to less than 40 nm, and thus contacts need to be smaller and have smaller gaps therebetween.
It may be difficult to overcome limitations of photolithography processes and ensure sufficient process margins because of resolution limits. However, electrical characteristics of the semiconductor devices need to be maintained despite the reduced areas of unit cells.
FIGS. 1 to 3 illustrate a conventional method of forming a contact structure. Referring to FIG. 1, an insulation layer 20 is formed on a substrate 10. After forming a first hole in the insulation layer 20, a first barrier layer 30 and a first metal layer are formed in the first contact hole to form a contact 40 in the insulation layer 20.
Referring to FIG. 2, a second insulation layer 50 is formed on the structure, including insulation layer 20 and contacts 40, and thereafter a second contact hole 55 is formed in the second insulation layer 50.
Referring to FIG. 3, a second barrier layer 60 and a second metal layer are formed in the second contact hole 55 in the second insulation layer 50, to form a second contact 70.
According to the conventional method, misalignments may be easily generated between the first contact 40 and the second contact 70. In order to avoid misalignments, various methods such as double patterning technology (DPT) may be utilized. However, the DPT may require a plurality of etching processes and photolithography processes.